MODULE 2 — ALU AND REGISTER FILE
This module builds the processor’s arithmetic and register-storage core. You will implement and verify a 32-bit ALU, then create a 32-register file with two read ports, synchronous write-back and protection for register x0.
Representative tests check every ALU operation, boundary values, zero detection, register reads and writes, reset behaviour and attempts to modify x0.
KEY OUTCOME
A verified ALU and register file ready for integration into the baseline processor.
ABOUT THE BOOK
eProjectCPU: From RTL to 104 MIPS is a practical engineering guide to designing, verifying and optimising a custom SystemVerilog processor for the Digilent Basys 3 FPGA. It follows the complete project journey from individual RTL modules and a single-cycle CPU through BRAM-aware multi-cycle and pipelined architectures, timing closure and physical FPGA measurement.
The book is currently being prepared for publication. Purchase information will be added here when the published edition becomes available.
Github
Explore the complete eProjectCPU source code, including the SystemVerilog RTL, self-checking testbenches, program files, FPGA constraints, Vivado scripts and supporting evidence used throughout the book. The repository contains the single-cycle, multi-cycle, five-stage and six-stage processor designs.