MODULE 3 — MEMORY, CONTROL AND THE SINGLE-CYCLE CPU This module connects the program counter, instruction memory, data memory, decoder and control unit into the first complete processor. You will trace instructions through the datapath and verify arithmetic, memory and control-flow behaviour with complete programs. The emphasis is on integration: checking addresses, decoded fields, control signals, ALU results, memory transfers and register write-back in signal-flow order. KEY OUTCOME A verified single-cycle CPU that provides the functional baseline for FPGA implementation and later redesign.
ABOUT THE BOOK
eProjectCPU: From RTL to 104 MIPS is a practical engineering guide to designing, verifying and optimising a custom SystemVerilog processor for the Digilent Basys 3 FPGA. It follows the complete project journey from individual RTL modules and a single-cycle CPU through BRAM-aware multi-cycle and pipelined architectures, timing closure and physical FPGA measurement.
The book is currently being prepared for publication. Purchase information will be added here when the published edition becomes available.
Github
Explore the complete eProjectCPU source code, including the SystemVerilog RTL, self-checking testbenches, program files, FPGA constraints, Vivado scripts and supporting evidence used throughout the book. The repository contains the single-cycle, multi-cycle, five-stage and six-stage processor designs.