MODULE 4 — FPGA IMPLEMENTATION AND TIMING ANALYSIS
This module takes the verified CPU from simulation into the Vivado implementation flow. You will synthesise, place and route the design for the Basys 3, then interpret utilisation, critical-path, WNS and TNS reports.
The failing 100 MHz baseline becomes useful engineering evidence: it identifies the physical limitation that motivates the BRAM-aware redesign.
KEY OUTCOME
A defensible FPGA implementation report and a clear explanation of why the original single-cycle architecture cannot meet the target clock.
ABOUT THE BOOK
eProjectCPU: From RTL to 104 MIPS is a practical engineering guide to designing, verifying and optimising a custom SystemVerilog processor for the Digilent Basys 3 FPGA. It follows the complete project journey from individual RTL modules and a single-cycle CPU through BRAM-aware multi-cycle and pipelined architectures, timing closure and physical FPGA measurement.
The book is currently being prepared for publication. Purchase information will be added here when the published edition becomes available.
Github
Explore the complete eProjectCPU source code, including the SystemVerilog RTL, self-checking testbenches, program files, FPGA constraints, Vivado scripts and supporting evidence used throughout the book. The repository contains the single-cycle, multi-cycle, five-stage and six-stage processor designs.