MODULE 6 — FIVE-STAGE PIPELINE AND HAZARD CONTROL This module overlaps instruction execution across IF, ID, EX, MEM and WB stages. You will add pipeline registers, forwarding paths, a one-cycle LOAD-use stall and branch-flush control. Worked cycle tables show exactly when values are forwarded, when the PC and IF/ID register are held, and how wrong-path instructions are invalidated after a taken branch. KEY OUTCOME A verified five-stage pipeline with correct data-hazard and control-hazard handling.
ABOUT THE BOOK
eProjectCPU: From RTL to 104 MIPS is a practical engineering guide to designing, verifying and optimising a custom SystemVerilog processor for the Digilent Basys 3 FPGA. It follows the complete project journey from individual RTL modules and a single-cycle CPU through BRAM-aware multi-cycle and pipelined architectures, timing closure and physical FPGA measurement.
The book is currently being prepared for publication. Purchase information will be added here when the published edition becomes available.
Github
Explore the complete eProjectCPU source code, including the SystemVerilog RTL, self-checking testbenches, program files, FPGA constraints, Vivado scripts and supporting evidence used throughout the book. The repository contains the single-cycle, multi-cycle, five-stage and six-stage processor designs.