MODULE 7 — SIX-STAGE PIPELINE AND ARCHITECTURE COMPARISON This module explores whether an additional pipeline stage can improve the processor’s clock frequency. You will examine the six-stage datapath, its extra registers and control requirements, then compare it fairly with the single-cycle, multi-cycle and five-stage designs. The evaluation combines Fmax, CPI, execution time and FPGA resources so that decisions are based on measured system performance rather than clock frequency alone. KEY OUTCOME An evidence-based architecture comparison that identifies the strongest design for the project workload.
ABOUT THE BOOK
eProjectCPU: From RTL to 104 MIPS is a practical engineering guide to designing, verifying and optimising a custom SystemVerilog processor for the Digilent Basys 3 FPGA. It follows the complete project journey from individual RTL modules and a single-cycle CPU through BRAM-aware multi-cycle and pipelined architectures, timing closure and physical FPGA measurement.
The book is currently being prepared for publication. Purchase information will be added here when the published edition becomes available.
Github
Explore the complete eProjectCPU source code, including the SystemVerilog RTL, self-checking testbenches, program files, FPGA constraints, Vivado scripts and supporting evidence used throughout the book. The repository contains the single-cycle, multi-cycle, five-stage and six-stage processor designs.