MODULE 1 — FOUNDATIONS, ISA AND VERIFICATION This module establishes the engineering foundations for eProjectCPU. It introduces the Vivado and SystemVerilog workflow, defines the custom 32-bit instruction set and explains how instructions are encoded, fetched and checked. You will build small RTL examples, create self-checking testbenches and learn how simulation evidence is used to prove correctness before the processor is assembled. By the end of the module, the ISA, development tools and verification method are ready for the CPU modules that follow. KEY OUTCOME A reproducible project environment, a documented custom ISA and a verification-first design workflow.
ABOUT THE BOOK
eProjectCPU: From RTL to 104 MIPS is a practical engineering guide to designing, verifying and optimising a custom SystemVerilog processor for the Digilent Basys 3 FPGA. It follows the complete project journey from individual RTL modules and a single-cycle CPU through BRAM-aware multi-cycle and pipelined architectures, timing closure and physical FPGA measurement.
The book is currently being prepared for publication. Purchase information will be added here when the published edition becomes available.
Github
Explore the complete eProjectCPU source code, including the SystemVerilog RTL, self-checking testbenches, program files, FPGA constraints, Vivado scripts and supporting evidence used throughout the book. The repository contains the single-cycle, multi-cycle, five-stage and six-stage processor designs.