Modules for EprojectCPU

Follow the complete eProjectCPU journey: from SystemVerilog foundations and verified processor modules to single-cycle integration, FPGA timing analysis, BRAM-aware redesign, pipelining and a physically measured 104 MIPS result.

Module 1: Foundations, ISA and Verification

Module 1: Foundations, ISA and Verification
Module 2: ALU and Register File

Module 2: ALU and Register File
Module 3: Memory, Control and the Single-Cycle CPU

Module 3: Memory, Control and the Single-Cycle CPU
Module 4: FPGA Implementation and Timing Analysis

Module 4: FPGA Implementation and Timing Analysis
Module 5: BRAM-Aware Multi-Cycle CPU

Module 5: BRAM-Aware Multi-Cycle CPU
Module 6: Five-Stage Pipeline and Hazard Control

Module 6: Five-Stage Pipeline and Hazard Control
Module 7: Six-Stage Pipeline and Architecture Comparison

Module 7: Six-Stage Pipeline and Architecture Comparison
Module 8: Physical FPGA Measurement — Reaching 104 MIPS

Module 8: Physical FPGA Measurement — Reaching 104 MIPS