MODULE 5 — BRAM-AWARE MULTI-CYCLE CPU This module redesigns execution around the synchronous behaviour of FPGA Block RAM. You will replace the long single-cycle path with a state-controlled processor that separates instruction fetch, decode, execution, memory access and write-back. A worked LOAD sequence shows how memory requests and responses are coordinated, while measured CPI and frequency reveal the trade-off between shorter paths and additional cycles. KEY OUTCOME A verified BRAM-aware multi-cycle CPU that maps naturally to FPGA memory resources.
ABOUT THE BOOK
eProjectCPU: From RTL to 104 MIPS is a practical engineering guide to designing, verifying and optimising a custom SystemVerilog processor for the Digilent Basys 3 FPGA. It follows the complete project journey from individual RTL modules and a single-cycle CPU through BRAM-aware multi-cycle and pipelined architectures, timing closure and physical FPGA measurement.
The book is currently being prepared for publication. Purchase information will be added here when the published edition becomes available.
Github
Explore the complete eProjectCPU source code, including the SystemVerilog RTL, self-checking testbenches, program files, FPGA constraints, Vivado scripts and supporting evidence used throughout the book. The repository contains the single-cycle, multi-cycle, five-stage and six-stage processor designs.