MODULE 8 — PHYSICAL FPGA MEASUREMENT: REACHING 104 MIPS This final module turns routed timing and simulated CPI into physical evidence. You will configure the FPGA clock, count retired instructions and elapsed cycles, and display the measured result on the Basys 3 seven-segment display. The final implementation operates at 119 MHz and reports approximately 104 million retired benchmark instructions per second. The result is kept workload-specific and is clearly separated from timing-derived estimates. KEY OUTCOME A physically demonstrated processor result supported by reproducible clocking, retirement and measurement evidence.
ABOUT THE BOOK
eProjectCPU: From RTL to 104 MIPS is a practical engineering guide to designing, verifying and optimising a custom SystemVerilog processor for the Digilent Basys 3 FPGA. It follows the complete project journey from individual RTL modules and a single-cycle CPU through BRAM-aware multi-cycle and pipelined architectures, timing closure and physical FPGA measurement.
The book is currently being prepared for publication. Purchase information will be added here when the published edition becomes available.
Github
Explore the complete eProjectCPU source code, including the SystemVerilog RTL, self-checking testbenches, program files, FPGA constraints, Vivado scripts and supporting evidence used throughout the book. The repository contains the single-cycle, multi-cycle, five-stage and six-stage processor designs.